1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory modules and related semiconductor memory devices. In particular, embodiments of the invention relate to modules enabling signal line short circuit testing of individual devices. Embodiments of the invention also relate to semiconductor memory devices in which signal line short circuit testing can be performed on individual terminals.
This application claims priority to Korean Patent Application No. 2006-0007852, filed on Jan. 25, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
As the respective sizes of electronic components in electronic devices become smaller, the degree of integration of circuit boards comprising the electronic components increases. Thus, the respective sizes of electronic devices comprising the circuit boards may be reduced. However, as packaged semiconductor memory devices decrease in size, and semiconductor memory devices are arranged more densely on a circuit board, bad connections increasingly arise between the circuit board and the semiconductor memory devices (i.e., components) mounted on the circuit board at terminals of the semiconductor memory devices. In addition, checking connections between semiconductor memory devices and a circuit board is difficult, so a convenient and precise technique for checking connections between semiconductor memory device terminals and the circuit board on which the semiconductor memory device is mounted is needed.
One technique for testing connections between component terminals and a corresponding circuit board is a boundary scanning technique, which was standardized in IEEE/ANSI 1491.1. The boundary scanning technique can be applied to logic circuits such as microprocessors or application specific integrated circuits (ASICs).
Figure (FIG.) 1 is a block diagram illustrating a semiconductor memory module that is tested using a conventional boundary scanning technique. The semiconductor memory module of FIG. 1 comprises electronic components 10a and 10b, a circuit board 20, and a wiring pattern 30. Electronic components 10a and 10b and circuit board 20 each comprise a test data input terminal TDI, a test mode selecting terminal TMS, a test clock terminal TCK, and a test data output terminal TDO (which may be referred to collectively as test terminals TDI, TMS, TCK and TDO). Test terminals TDI, TMS, TCK and TDO are only used for performing tests, and test terminals TDI, TMS, TCK and TDO of each element (such as electronic component 10a and circuit board 20) in the semiconductor memory module of FIG. 1 are respectively connected to corresponding test terminals TDI, TMS, TCK and TDO of another element(s) of the semiconductor memory module of FIG. 1 by wiring pattern 30 formed on circuit board 20.
Each of electronic components 10a and 10b comprises a test circuit comprising a plurality of BS cells 40, an instruction register (IR) 50, a bypass register 60, and a tap controller 70. In electronic component 10a, for example, BS cells 40 are arranged so that they each correspond to a terminal connected to a core portion 80, and each of BS cells 40 also has a latching function. Instruction register 50 recognizes a test instruction received from test data input terminal TDI. Bypass register 60 outputs data supplied from test data input terminal TDI directly to test data output terminal TDO. In addition, tap controller 70 decodes a test mode signal received from test mode selecting terminal TMS.
When a plurality of electronic components 10a and 10b are mounted on circuit board 20, as shown in FIG. 1, since test data output terminal TDO of electronic component 10a is connected to test data input terminal TDI of the adjacent electronic component 10b, a scanning path loop (indicated in FIG. 1 by a bold, solid line) is formed in circuit board 20.
A controller (not shown), which is disposed outside of and is connected to circuit board 20, controls the test terminals of electronic components 10a and 10b and circuit board 20 so that electronic components 10a and 10b and circuit board 20 can receive a test instruction and an input pattern through test data input terminal TDI.
Each test circuit of electronic components 10a and 10b operates in response to the input instruction and the input pattern and outputs an output pattern through its test data output terminal TDO.
The controller then compares the output pattern to an expected pattern to check the state of connections between the terminals of electronic components 10a and 10b and circuit board 20 and thereby detects defects such as soldering defects related to the terminals or mounting location defects related to electronic components 10a and 10b. 
However, the boundary scanning technique described above requires terminals dedicated for performing the test and a plurality of test circuits arranged in the electronic components, which affects chip size. In addition, the boundary scanning technique requires a special algorithm for applying the test instruction and the input pattern to enter into the test mode.
In addition, a memory system comprises a memory control circuit and a plurality of memory modules, wherein each of the memory modules comprises a plurality of semiconductor memory devices. Each data signal line of a plurality of data signal lines is directly connected to one of the semiconductor memory devices of the plurality of semiconductor memory devices of the memory module in a pin to pin method. However, address signals, instruction signals, and control signals are applied to the plurality of semiconductor memory devices via a single signal line.
Short circuit tests can be performed on individual pins of semiconductor memory devices that are each connected to a respective data signal line of a plurality of data signal lines in a pin to pin method. However, when a plurality of address signals are applied to a plurality of semiconductor memory devices via a single signal line, as in the conventional boundary scanning technique, testing whether an individual pin connected to the single signal line has been short-circuited is impossible because, when one pin is short-circuited, all of the pins connected to that line are short-circuited. In addition, when a connection problem arises, it is impossible to individually test the semiconductor memory devices in order to locate the problem.